1. Field of the Invention
This invention relates to a network for efficient communication within a digital system and, in particular, to a multi-stationed grid of stations and interconnecting buses providing a high-speed pipelined and configurable communication network for a field-programmable gate array.
2. History of the Prior Art
Digital systems can be implemented using off-the-shelf integrated circuits. However, system designers can often reduce cost, increase performance, or add capabilities by employing in the system some integrated circuits whose logic functions can be customized. Two common kinds of customizable integrated circuits in digital systems are application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs).
ASICs are designed and manufactured for a particular application. An ASIC includes circuits selected from a library of small logic cells. A typical ASIC also includes large special-purpose blocks that implement widely-used functions, such as a multi-kilobit random-access memory (RAM) or a microprocessor. The logic cells and special-function blocks are placed at suitable locations on the ASIC and connected by means of wiring.
Application-specific integrated circuits (ASICs) have several advantages. Because an ASIC contains only the circuits required for the application, it has a small die size. An ASIC also has low power consumption and high performance.
ASICs have some disadvantages. It takes a lot of time and money to design ASICs because the design process is complex. Creating prototypes for an ASIC is complex as well, so prototyping also takes a lot of time and money.
Field-programmable gate arrays (FPGAs) are another kind of customizable integrated circuit that is common in digital systems. An FPGA is a general-purpose device. It is meant to be configured for a particular application by the system designer.
FIG. 21 provides a schematic diagram of a portion of a conventional FPGA. The FPGA includes a plurality of general-purpose configurable logic blocks, a plurality of configurable special-purpose blocks, and a plurality of routing crossbars. In an example, each logic block, such as logic block 101, may include a plurality of four-input lookup tables (LUTs) and a plurality of configurable one-bit sequential cells, each of which can be configured as a flip-flop or a latch. A configurable special-purpose block, such as special-purpose blocks 151 and 155, implements a widely-used function. An FPGA may have more than one type of special-purpose block.
The routing crossbars form a two-dimensional routing network that provides configurable connections among the logic blocks and the special-purpose blocks. In the illustrative FPGA, each routing crossbar is connected to the nearest-neighbor routing crossbars in four directions and to either a logic block or a special-purpose block. For example, routing crossbars 125 and 100 are connected by buses 104. In the example FPGA, each logic block, such as logic block 101, is connected to one routing crossbar, such as routing crossbar 100. Special-purpose blocks are typically much larger than logic blocks and typically have more input and output signals, so a special-purpose block, such as special-purpose block 151, may be connected by a plurality of buses to a plurality of routing crossbars, such as routing crossbars 130-133.
The logic blocks, special-purpose blocks, and routing crossbars contain circuitry (called configuration memory) which allows their operation to be configured. A user's design is implemented in the FPGA by setting the configuration memory appropriately. Several forms of configuration memory are used by contemporary FPGAs, the most common form being static random-access memory. Configuring an FPGA places it in a condition to perform a specific one of many possible applications.
Field-programmable gate arrays (FPGAs) have advantages over application-specific integrated circuits (ASICs). Prototyping an FPGA is a relatively fast and inexpensive process. Also, it takes less time and money to implement a design in an FPGA than to design an ASIC because the FPGA design process has fewer steps.
FPGAs have some disadvantages, the most important being die area. Logic blocks use more area than the equivalent ASIC logic cells, and the switches and configuration memory in routing crossbars use far more area than the equivalent wiring of an ASIC. FPGAs also have higher power consumption and lower performance than ASICs.
The user of an FPGA may improve its performance by means of a technique known as pipelining. The operating frequency of a digital design is limited, in part, by the number of levels of look-up tables that data must pass through between one set of sequential cells and the next. The user can partition a set of look-up tables into a pipeline of stages by using additional sets of sequential cells. This technique may reduce the number of levels of look-up tables between sets of sequential cells and, therefore, may allow a higher operating frequency. However, pipelining does not improve the performance of FPGAs relative to that of ASICs, because the designer of an ASIC can also use the pipelining technique.
It would be desirable to provide circuitry which allows the configurability, low time and cost of design, and low time and cost of prototyping typical of an FPGA while maintaining the high performance, low die area, and low power expenditure of an ASIC. Specialized special-purpose blocks might help the integrated circuit resemble an ASIC by having relatively high performance and relatively low die area. The integrated circuit might retain most of the benefits of an FPGA in being relatively configurable and in needing low time and cost for design and low time and cost for prototyping.
However, a conventional FPGA routing crossbar network cannot accommodate the high data bandwidth of the special-purpose blocks in such an integrated circuit. The operating frequency of signals routed through a routing crossbar network is relatively low. A user may employ pipeline registers to increase the frequency somewhat, but doing so consumes register resources in the logic blocks. Building an FPGA with a much greater number of routing crossbars than usual would increase the data bandwidth, but it is impractical because routing crossbars use a large area.